半導体デバイスを中心に、社会インフラの電化・電動化を支えるキーコンポーネントや、機器の動作状態や環境情報をデジタル化するセンシング、太陽光パネルや燃料電池などのグリーン電力活用に関する研究開発を行っています。物理モデル解析やデバイス・プロセス技術を駆使し、革新的なソリューション創生に取り組んでいます。
電磁気学、物性物理、半導体デバイス・プロセス、デバイス設計・解析・制御技術、モデリング・シミュレータ、SOFC、再エネ電力融通
Publishing Academic Papers:
N. Watanabe, et al., "Impact of Cell Layout on On-state and Dynamic Characteristics of N-channel SiC IGBTs" Proc. 34th International Symposium on Power Semiconductor Devices and IC's, pp. 85-88, 2022.
https://doi.org/10.1109/ISPSD49238.2022.9813599
Abstract: The conductivity-modulation enhancement of nchannel SiC insulated-gate bipolar transistors (IGBTs) with different device cell layouts has been investigated. By utilizing the box cell layout, the specific differential on-resistance was reduced by 35%, while the turn-off loss increased only slightly (up to 7%). This implies that the box layout can effectively enhance the carrier concentration near the emitter region in the on-state. Also, SiC IGBTs fabricated with the box layout properly operated without latch-up phenomenon up to 300 A/cm² switching. SiC IGBTs can significantly reduce the on-voltage with only a small switching loss increase by utilizing the box layout.
N. Watanabe, et al., "Power Loss Reduction of N-Channel 10-kV SiC IGBTs With Box Cell Layout" IEEE Trans. Electron Devices, vol. 70, no. 7, pp. 3768-3773, July. 2023.
https://doi.org/10.1109/TED.2023.3279799
Abstract: We investigated the power loss reduction of an n-channel 4H-silicon carbide (SiC) insulated-gate bipolar transistor (IGBT) with a blocking voltage of 10 kV by utilizing a box cell layout, which can enhance the conductivity modulation, instead of a conventional string cell layout. The box cell layout significantly reduced the on-voltage of SiC IGBTs, which are a 35% and 29% reduction in the specific differential on-resistance at 25 °C and 150 °C, respectively. Although enhancing the conductivity modulation should increase the turn-off loss, it has increased slightly, by 10% at 25 °C and by 5% at 150 °C with a load current of 250 A/cm² because the box cell layout can enhance the stored carrier, particularly near the emitter in the on-state. In contrast to the turn-off loss, turn-on loss was reduced by the box cell layout due to the enhancement of electron injection from the emitter, resulting in a lower total switching loss in comparison to a string-layout device. A lower on-voltage and switching loss of SiC IGBTs have both been achieved as a result of the box cell layout enhancing conductivity modulation enhancement.
Y. Mori, et al., "Device design to achieve low loss and high short-circuit capability for SiC Trench MOSFET" Proc. 33rd International Symposium on Power Semiconductor Devices and IC's, pp. 111-114, 2021.
https://doi.org/10.23919/ISPSD50666.2021.9452303
Abstract: The trade-off between low on-resistance and high short-circuit (SC) capability crucial for silicon carbide metal-oxide-semiconductor (MOS) field-effect transistors. To break this trade-off, we clarified the design parameters that are key in improving SC capability and confirmed that our trench-etched double-diffused MOS (TED-MOS) can be suitably designed using its unique parameters to achieve low on-resistance while maintaining high SC capability.
H. Shimizu, et al., " Proposal of Vertical-channel Fin-SiC MOSFET toward Future Device Scaling" Proc. 35th International Symposium on Power Semiconductor Devices and IC's, pp. 1-4, 2023.
https://doi.org/10.1109/ISPSD57135.2023.10147561
Abstract: We propose a new SiC trench MOSFET suitable for achieving both low loss and high reliability. This structure, called a VC Fin-SiC, is characterized by a fin-shaped trench, and by adopting a wide channel formed on the sidewall of the fin and a narrow JFET with high dopant concentration, it achieves both low on-resistance and high reliability. In this work, these design concepts are verified through simulation and actual device fabrication. Because the VC Fin-SiC has channels directly above the JFET structure, the performance can be easily improved by scaling the fin-pitch and channel length, and it will be one of the most promising structures in the future.
M.Shiraishi, et al.," Side Gate HiGT with Low dv/dt Noise and Low Loss "
Proc. 28th International Symposium on Power Semiconductor Devices and IC's (ISPSD)
Abstract: This paper presents a novel side gate HiGT (High-conductivity IGBT) that incorporates historical changes of gate structures for planar and trench gate IGBTs. Side gate HiGT has a side-wall gate, and the opposite side of channel region for side-wall gate is covered by a thick oxide layer to reduce Miller capacitance (Cres). In addition, side gate HiGT has no floating p-layer, which causes the excess Vge overshoot. The proposed side gate HiGT has 75% smaller Cres than the conventional trench gate IGBT. The excess Vge overshoot during turn-on is effectively suppressed, and Eon + Err can be reduced by 34% at the same diode’s recovery dv/dt. Furthermore, side gate HiGT has sufficiently rugged RBSOA and SCSOA.
T.Furukawa, et al.,"High power density Side-gate HiGT Modules with Sintered Cu Having Superior High-temperature Reliability to Sintered Ag"
Proc. 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)
Abstract: In this study, sintered Cu is shown to have superior reliability to that of sintered Ag, in a high-temperature thermal cycle test up to 200˚C and superior power cycle durability at a maximum junction temperature of 175˚C. A 1700-V low-stray-inductance dual module made with sintered Cu and a leading-edge side-gate HiGT (High-conductivity IGBT), are shown to have high power density with low loss and ten times higher power cycle durability compared with Pb-rich solder.
T.Miyoshi, et al.,"Dual side-gate HiGT breaking through the limitation of IGBT loss reduction"
Proc. Power Conversion and Intelligent Motion Europe 2017
Abstract: A novel Dual side-gate HiGT (High-conductivity IGBT) with an extremely small feedback capacitance (Cres) and a function of controllable conductivity modulation was proposed. Dynamic control of stored carrier concentration right before switching by tandem drive of the dual gate makes it possible to further reduce switching loss with conventional single gate IGBTs. Compared with the single gate drive on conventional side-gate HiGT, the dual side-gate HiGT further reduces loss during turn-off and turn-on by 31% and 12%, respectively. As a result, an inverter system with dual side-gate HiGTs can reduce power dissipation by a further 15% and break through the performance limit imposed by conventional IGBTs.
M. Masunaga, et al., "4H-SiC CMOS Transimpedance Amplifier of Gamma-Irradiation Resistance Over 1 MGy." IEEE Trans. Electron Devices, vol. 67, no. 1, pp. 224-229, Jan. 2020.
https://ieeexplore.ieee.org/document/8930609
Abstract: A transimpedance amplifier (TIA)-with gamma-irradiation resistance of over 1 MGy-based on a novel 4H-SiC complementary MOS (CMOS) technology was fabricated. This TIA is robust enough to be applied in measuring instruments installed in nuclear power plants or other harshly irradiated environments. The SiC CMOS transistors comprising the TIA feature a thin (8-nm-thick) gate oxide to reduce the threshold-voltage shift (Vth) due to irradiation by more than 90% compared with that of the conventional transistors. Oxynitride protection formed at the SiC-SiO2 interface in the thin gate-oxide region suppresses the deterioration of mobility by interface traps generated by the gamma radiation. The TIA consisting of these SiC-CMOS transistors operated properly up to at least 1.2 MGy without an increase in the offset voltage, although its open-loop gain was degraded due to deteriorated mobility of the p-channel metal-oxide-semiconductor field-effect transistor (MOSFET). On the other hand, increasing the drain leakage current in the nonactive region impeded further improvement of the SiC TIA under a high integral dose. To decrease the drain leakage current, a structure with a high doping concentration layer between the source and the drain in the nonactive region was fabricated. The structure stops the parasitic transistor turning on and the trap-assisted current increasing. The leakage current of the improved structure is about 42% lower than that of a conventional structure.
M. Masunaga, " Low-Frequency Noise of 4H-SiC CMOS Technology for Analog ICs." IEEE Trans. Electron Devices, vol. 70, no. 6, pp. 3228–3233, June 2023.
https://ieeexplore.ieee.org/document/10113136/
Abstract: To design low-noise analog ICs for nuclear power plants, low-frequency noise (LFN) of 4H-SiC CMOS technology was studied in the frequency range of 3 Hz–10 kHz at room temperature. The LFN of the long-channel MOS devices was systematically studied in terms of gate length, gate width, drain current, and drain voltage. It was found to follow the noise model for carrier number fluctuation regardless of conduction type. In addition, the standard deviation of spectral noise density (Sid) at 10 Hz for the p-channel MOS was experimentally found to be 4.6× larger than that for the n-channel MOS. This was caused by the increase in random telegraph noise (RTN) caused by oxide hole traps with nitrogen incorporation at the SiO2/SiC interface. The flicker noise coefficient (KF) in the noise model was estimated to be 4.1×10−26 and 1.2×10−27s1-EFA2-AFF for the n- and p-channel MOS, respectively.
M. Masunaga, et al., "Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments" Appl. Phys. Lett., vol. 124, 042103, Jan. 2024.
https://doi.org/10.1063/5.0184689
Abstract: To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in the range of 25–350 °C. Ea around 300 °C was 0.7 eV for nMOS and 0.66 eV for pMOS, which was about twice as high as that below 150 °C and did not differ greatly depending on the conductivity type. The gate dielectric breakdown mechanism shifted from the 1/E model to the E model as the temperature rose, and this is thought to have caused the Ea to change. The field acceleration factor in the E model at 300 °C was 2.7 and 2.3 cm/MV for nMOS and pMOS, respectively. The maximum operating electric fields of nMOS and pMOS for a 100-year lifetime are 6.8 and −7.2 MV/cm, which are over 25% lower than the fields at room temperature, mainly due to a shift in the dominant breakdown model. A more conservative failure time design will be required for SiC-ICs exposed to high temperatures.
Y. Sasago, et al., "Thin-Film SOFC Enabling Low-Temperature and Low-Hydrogen-Concentration Operation," ECS Trans. 103, 1705 (2021).
http://dx.doi.org/10.1149/10301.1705ecst
Abstract: A thin-film solid oxide fuel cell (SOFC) was developed on an anodic aluminum oxide substrate. A dense yttria-stabilized zirconia (YSZ) layer with a thickness of 290 nm on a platinum anode layer, and a cathode layer of gadolinia-doped ceria and platinum (10:90) with a thickness of 20 nm was deposited on the YSZ layer. As a result, the output power density of 203 mW/cm² at 453°C was achieved even when using 3%-concentration hydrogen. The high power density indicates that our SOFC can operate using the low-concentration hydrogen from hydrous bioethanol at low temperatures.
J. Tsunoda, et al., “Deterioration-detection and Failure-detection Algorithms for Storage Batteries Using Hysteresis Characteristics”, Proc. IEEE Electrical Energy Storage Applications and Technologies (EESAT), 2022
https://ieeexplore.ieee.org/document/9998032/
Abstract: We developed deterioration-detection and failure-detection algorithms for a storage battery and succeeded in declaring the timing of future failure by using the hysteresis characteristics of the storage battery and voltage change of only a few seconds. The greatest advantage of these algorithms is using the change in hysteresis caused by the physical phenomenon of the storage battery, i.e., the change in resistance due to deterioration and difference in thermal reaction energy during discharging. We evaluated storage batteries by linking these hysteresis characteristics with voltage change after charging and discharging. By capturing the difference in or ratio of the voltage change after charging and discharging, we could determine the health and failure potential of a storage battery. For cells with failure potential, we could detect the failure timing six months in advance and we experimentally confirmed that the cell actually failed.
European Conference on Silicon Carbide and Related Materials (ECSCRM) 2018
Best Paper Award
https://warwick.ac.uk/fac/sci/eng/ecscrm2018/programme/awards/
International Symposium on Power Semiconductor Devices and IC's (ISPSD)
ISPSD2017 THE OHMI BEST PAPER AWARD
Power Conversion and Intelligent Motion Europe
PCIM Europe 2017 Young Engineer Award 2017
第76回電気学術振興賞 進歩賞
低損失・低dv/dtノイズを実現するサイドウォールゲート構造を有するIGBTパワーモジュールの開発
https://www.iee.jp/blog/award2020/
第20回ひょうごSPring-8賞
SiCパワーデバイス実用化に向けた動作中デバイスにおける結晶欠陥可視化技術の開発
https://web.pref.hyogo.lg.jp/sr11/ie03_000000168.html
第78回電気学術振興賞 進歩賞
高レベルな放射線環境に耐える高精度SiC-CMOSアンプの開発
https://www.iee.jp/blog/award2022/
ニュースリリース：2021年1月26日
耐久性と低消費電力特性を両立した新構造SiCパワーデバイス「TED-MOS」を製品化
https://www.hitachi.co.jp/New/cnews/month/2021/01/0126.html
日立研究開発ニュース＆イベント：2021年8月19日
SiCパワーデバイス「TED-MOS」の物理モデルに基づく高自由度設計技術を開発
https://www.hitachi.co.jp/rd/news/topics/2021/2108_sic.html
ニュースリリース：2021年12月21日
日立パワーデバイスが、スイッチング損失を従来比で約30％低減した高耐久・低損失の1.7kVフルSiCモジュールを製品化
https://www.hitachi.co.jp/New/cnews/month/2021/12/1221.html
日立技術の展望：2017 Vol.99 No.1
低損失・低ノイズIGBTサイドゲートHiGT
https://www.hitachihyoron.com/jp/archive/2010s/2017/01/24/index.html#sec09
NIKKEI ELECTORNICS 2018.01
新型IGBTとSiCダイオードで、「フルSiC」並みの低損失
NIKKEI ELECTORNICS 2018.03
焼結Cuでパワーデバイスを実装、信頼性10倍、熱抵抗60％減
ニュースリリース：2017年9月14日
過酷環境下で安定動作するSiC-CMOS集積回路技術を世界で初めて開発
http://www.hitachi.co.jp/New/cnews/month/2017/09/0914.pdf
ニュースリリース：2022年10月19日
日立が、再エネ発電設備と自己託送制度を利用した
CO2削減を支援する多拠点エネルギーマネジメントサービス事業に着手
https://www.hitachi.co.jp/New/cnews/month/2022/10/1019b.html
