半導体デバイスを中心に、社会インフラの電化・電動化を支えるキーコンポーネントや、機器の動作状態や環境情報をデジタル化するセンシング、太陽光パネルや燃料電池などのグリーン電力活用に関する研究開発を行っています。物理モデル解析やデバイス・プロセス技術を駆使し、革新的なソリューション創生に取り組んでいます。
電磁気学、物性物理、半導体デバイス・プロセス、デバイス設計・解析・制御技術、モデリング・シミュレータ、SOFC、再エネ電力融通
Publishing Academic Papers:
N. Watanabe, et al., "First Demonstration of Trench-shaped 6.5-kV n-channel SiC IGBT with Trench-etched Double-diffused MOS (TED-MOS) Structure" in Proceedings of the International Electron Devices Meeting (IEDM), 2023,
https://doi.org/10.1109/IEDM45741.2023.10413693
Abstract: We report the first experimental demonstration of trench-shaped 6.5-kV SiC IGBTs. The trench-etched double-diffused MOS (TED-MOS) structure was employed to improve the electron injection from the emitter due to its fin-shaped gate channel while keeping the electric field of a gate oxide sufficiently low. The SiC IGBT with the TED-MOS structure had an on-voltage of 4.8 V at the collector current of 200 A/cm 2 at 25 °C. The specific differential on-resistance at this point was 6.6 mΩ•cm 2 , which was around three times lower than that of the conventional planar-gate device. It also had a smaller feedback capacitance, leading to a reduction of the turn-off loss. The turn-on loss was also reduced due to the electron injection enhancement. The SiC IGBT exhibited both a lower on-voltage and switching loss by utilizing the TED-MOS structure.
T. Suematsu, et al., " Development of Vertical-Channel Fin-SiC MOSFET for 3.3 kV Applications" Proc. 36th International Symposium on Power Semiconductor Devices and IC's, pp. 1-4, 2024.
https://doi.org/10.1109/ISPSD59661.2024.10579566
Abstract: We have developed a 3.3 kV SiC Vertical-Channel Fin MOSFET, original structure named VC Fin-SiC. The JFET structure was optimized using TCAD simulation to achieve low on-resistance and high reliability. Our evaluation of the static and switching properties demonstrate that VC Fin-SiC can achieve low on-resistance with high threshold voltage and small switching loss with fast turn-on even for high voltage applications thanks to its structural superiority.
T. Suto, et al., " Circuit Simulation Model with Design Parameters for SiC-MOSFET" Proc. 36th International Symposium on Power Semiconductor Devices and IC's, pp. 80-83, 2024.
https://doi.org/10.1109/ISPSD59661.2024.10579569
Abstract: We propose a physics-based model incorporating the interaction between MOSFET and JFET in SiC, which allows for the explicit setting of design parameters. Developed in this research, the model aims at estimating worst- case scenarios and accounting for significant variations. This model is applied to a commercial SiC MOSFET as demonstration. The results align closely with measured waveforms under various conditions. The results indicates this model is expected to be used even for short-circuit calculations.
Y. Takeuchi, et al., "Side gate HiGT that realizes the high power density of IGBT modules"
Proc. 6th International Electric Vehicle Technology Conference (EVTeC 2023)
Abstract: This paper describes a developed high power density 750 V/800 A 6-in-1 IGBT module suitable for xEV application. The developed module has features of the copper lead structure for reduction of thermal resistance and the epoxy resin encapsulation for improving thermal stress reliability. In order to reduce power loss, side gate HiGTs and U-SFDs were installed to achieve both low switching loss and low noise. Furthermore, side gate HiGTs have a superior feature of a wide RBSOA necessary for the latest high power density IGBT modules. By integrating the above technologies, the developed module can achieve a -29% smaller footprint and a -27% lighter weight while keeping the same output current as our conventional IGBT module. Consequently, the developed module can realize a +70% higher power density than the conventional one.
K. Tani, et al., "Cascade-connected low-voltage MOSFETs operating as high-voltage MOSFET"
Proc. 36th International Symposium on Power Semiconductor Devices and IC's (ISPSD 2024)
Abstract: Power integrated circuits require integrating devices with multiple rated voltages, but integration of high-voltage devices poses challenges such as the need for special wafer specifications and an increase in process steps. We propose a monolithically integrated cascade-connected low-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) operating as one high-voltage MOSFET, consisting only of low-voltage enhancement MOSFETs. In cascade-connected n-MOSFETs, two enhancement p-MOSFETs with gates and drains connected to each other are connected between the gates of the enhancement n-MOSFETs in series. The cascade-connected p-MOSFETs have a structure in which p-MOSFETs in the cascade-connected n -MOSFETs are replaced with n -MOSFETs, and n-MOSFETs are replaced with p -MOSFETs, and the connection relationships between the gate, drain, and source are the same. We confirmed our cascade-connected MOSFETs' static characteristics and switching operation as a high-voltage MOSFET. The breakdown voltage of the cascade-connected MOSFETs increased in proportion to the number of series connections, reaching over 800 V for 29 series. From the above results, cascade-connected MOSFETs are promising for integrating devices with various rated voltages..
T. Hirao, et al., "6.5 kV innovative silicon power device (i-Si) module with high power density and low loss by stored carrier control"
Proc. PCIM Europe 2024
Abstract: This paper describes a demonstration of the low loss performance of a 6.5 kV innovative silicon power device (i-Si) module. The i-Si module uses stored carrier control to both the switching device and free wheel diode, which is made entirely from silicon. A 6.5 kV 800 A i-Si module was fabricated at a size of 130 mm × 140 mm. Despite having a package size 2/3 that of a conventional 6.5 kV 750 A IGBT, the fabricated i-Si module has 40% lower loss, similar to that of SiC MOSFETs.
M. Masunaga, et al., "4H-SiC CMOS Transimpedance Amplifier of Gamma-Irradiation Resistance Over 1 MGy." IEEE Trans. Electron Devices, vol. 67, no. 1, pp. 224-229, Jan. 2020.
https://ieeexplore.ieee.org/document/8930609
Abstract: A transimpedance amplifier (TIA)-with gamma-irradiation resistance of over 1 MGy-based on a novel 4H-SiC complementary MOS (CMOS) technology was fabricated. This TIA is robust enough to be applied in measuring instruments installed in nuclear power plants or other harshly irradiated environments. The SiC CMOS transistors comprising the TIA feature a thin (8-nm-thick) gate oxide to reduce the threshold-voltage shift (Vth) due to irradiation by more than 90% compared with that of the conventional transistors. Oxynitride protection formed at the SiC-SiO2 interface in the thin gate-oxide region suppresses the deterioration of mobility by interface traps generated by the gamma radiation. The TIA consisting of these SiC-CMOS transistors operated properly up to at least 1.2 MGy without an increase in the offset voltage, although its open-loop gain was degraded due to deteriorated mobility of the p-channel metal-oxide-semiconductor field-effect transistor (MOSFET). On the other hand, increasing the drain leakage current in the nonactive region impeded further improvement of the SiC TIA under a high integral dose. To decrease the drain leakage current, a structure with a high doping concentration layer between the source and the drain in the nonactive region was fabricated. The structure stops the parasitic transistor turning on and the trap-assisted current increasing. The leakage current of the improved structure is about 42% lower than that of a conventional structure.
M. Masunaga, et al., "Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments" Appl. Phys. Lett., vol. 124, 042103, Jan. 2024.
https://doi.org/10.1063/5.0184689
Abstract: To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in the range of 25–350 °C. Ea around 300 °C was 0.7 eV for nMOS and 0.66 eV for pMOS, which was about twice as high as that below 150 °C and did not differ greatly depending on the conductivity type. The gate dielectric breakdown mechanism shifted from the 1/E model to the E model as the temperature rose, and this is thought to have caused the Ea to change. The field acceleration factor in the E model at 300 °C was 2.7 and 2.3 cm/MV for nMOS and pMOS, respectively. The maximum operating electric fields of nMOS and pMOS for a 100-year lifetime are 6.8 and −7.2 MV/cm, which are over 25% lower than the fields at room temperature, mainly due to a shift in the dominant breakdown model. A more conservative failure time design will be required for SiC-ICs exposed to high temperatures.
Y. Sasago, et al., "Thin-Film SOFC Enabling Low-Temperature and Low-Hydrogen-Concentration Operation," ECS Trans. 103, 1705 (2021).
http://dx.doi.org/10.1149/10301.1705ecst
Abstract: A thin-film solid oxide fuel cell (SOFC) was developed on an anodic aluminum oxide substrate. A dense yttria-stabilized zirconia (YSZ) layer with a thickness of 290 nm on a platinum anode layer, and a cathode layer of gadolinia-doped ceria and platinum (10:90) with a thickness of 20 nm was deposited on the YSZ layer. As a result, the output power density of 203 mW/cm² at 453°C was achieved even when using 3%-concentration hydrogen. The high power density indicates that our SOFC can operate using the low-concentration hydrogen from hydrous bioethanol at low temperatures.
J. Tsunoda, et al., "Deterioration-detection and Failure-detection Algorithms for Storage Batteries Using Hysteresis Characteristics", Proc. IEEE Electrical Energy Storage Applications and Technologies (EESAT), 2022
https://ieeexplore.ieee.org/document/9998032/
Abstract: We developed deterioration-detection and failure-detection algorithms for a storage battery and succeeded in declaring the timing of future failure by using the hysteresis characteristics of the storage battery and voltage change of only a few seconds. The greatest advantage of these algorithms is using the change in hysteresis caused by the physical phenomenon of the storage battery, i.e., the change in resistance due to deterioration and difference in thermal reaction energy during discharging. We evaluated storage batteries by linking these hysteresis characteristics with voltage change after charging and discharging. By capturing the difference in or ratio of the voltage change after charging and discharging, we could determine the health and failure potential of a storage battery. For cells with failure potential, we could detect the failure timing six months in advance and we experimentally confirmed that the cell actually failed.
T. Kohno, et al., "PV Prediction Method Responding to Power Fluctuations Based on Unique Weather Classification Using PV Model and Neural Network", Proc. IEEE 52nd Photovoltaic Specialist Conference (PVSC), 2024
10.1109/PVSC57443.2024.10749572
https://doi.org/10.1109/PVSC57443.2024.10749572
Abstract: A PV prediction method based on the unique weather classification was developed. This method is useful for applications where the effect of equalizing the number of sites cannot be expected, such as self-consignment. In this method, the current and voltage measured by the inverter are converted into the estimated irradiation and temperature using the PV mathematical model. The feature of this method is to learn the relationship between each of the estimated irradiation and temperature and each of the irradiation and temperature forecasts given by the weather provider. This learning is performed on the inclination of the ground mounted PV array, errors due to the installation position and angle of each power plant are suppressed. By applying a neural network to the one-hour weather code sent by the the weather provider and the estimated irradiation's fluctuation data, the weather code is subdivided into a unique weather classification corresponding to PV power fluctuation. Firstly, we created correction coefficients for each weather classification using the 5.4 kW system that can measure current and voltage in 1-minute increments. Next, the correction factor was fine-tuned for each large-scale power plant. For data of more than 300 days in five MW-class large-scale power plants, the mean absolute error of the proposed method was evaluated using the forecast at 7 o'clock on the previous day or the same day. As a result, the average was 5%, and the worst was 8%, which was a good result.
European Conference on Silicon Carbide and Related Materials (ECSCRM) 2018
Best Paper Award
https://warwick.ac.uk/fac/sci/eng/ecscrm2018/programme/awards/
EVTeC 2023 Young Investigator Awards
https://www.evtec.jp/2023/award.html
第76回電気学術振興賞 進歩賞
低損失の限界性能を打開するデュアルゲート型IGBTの開発
https://www.iee.jp/blog/award2024-2/
第20回ひょうごSPring-8賞
SiCパワーデバイス実用化に向けた動作中デバイスにおける結晶欠陥可視化技術の開発
https://web.pref.hyogo.lg.jp/sr11/ie03_000000168.html
第78回電気学術振興賞 進歩賞
高レベルな放射線環境に耐える高精度SiC-CMOSアンプの開発
https://www.iee.jp/blog/award2022/
ニュースリリース：2021年1月26日
耐久性と低消費電力特性を両立した新構造SiCパワーデバイス「TED-MOS」を製品化
https://www.hitachi.co.jp/New/cnews/month/2021/01/0126.html
日立研究開発ニュース＆イベント：2021年8月19日
SiCパワーデバイス「TED-MOS」の物理モデルに基づく高自由度設計技術を開発
https://www.hitachi.co.jp/rd/news/topics/2021/2108_sic.html
ニュースリリース：2021年12月21日
日立パワーデバイスが、スイッチング損失を従来比で約30％低減した高耐久・低損失の1.7kVフルSiCモジュールを製品化
https://www.hitachi.co.jp/New/cnews/month/2021/12/1221.html
日立技術の展望：2017 Vol.99 No.1
低損失・低ノイズIGBTサイドゲートHiGT
https://www.hitachihyoron.com/jp/archive/2010s/2017/01/24/index.html#sec09
NIKKEI ELECTORNICS 2018.01
新型IGBTとSiCダイオードで、「フルSiC」並みの低損失
NIKKEI ELECTORNICS 2018.03
焼結Cuでパワーデバイスを実装、信頼性10倍、熱抵抗60％減
ニュースリリース：2017年9月14日
過酷環境下で安定動作するSiC-CMOS集積回路技術を世界で初めて開発
http://www.hitachi.co.jp/New/cnews/month/2017/09/0914.pdf
ニュースリリース：2022年10月19日
日立が、再エネ発電設備と自己託送制度を利用した
CO2削減を支援する多拠点エネルギーマネジメントサービス事業に着手
https://www.hitachi.co.jp/New/cnews/month/2022/10/1019b.html
